Mobile electronic devices require low standby power for long battery life. One method to reduce standby power is to use the body effect of a transistor that is not in use to reduce the off current. When the body voltage of an NMOS transistor is lowered the body effect causes the vt of the transistor to rise resulting in lower off current. To be able to adjust the body voltage of a NMOS transistor in a conventional CMOS device built on p-type substrate, the NMOS transistor must be constructed in an isolated p-well.
The logic state of NMOS transistors in some circuits may be upset by noise injected into the substrate when transistors switch in close proximity. To avoid this problem it is desirable to place NMOS transistors whose logic state may be upset or the transistors that may cause upset in an isolated p-well.
Other components such as gate to p-well capacitors and NPN bipolar transistors may also be constructed with isolated p-wells. The bottom electrode of gate-to-p-well capacitors built in core p-wells is always at a fixed voltage because the core p-wells are shorted to the p-type substrate whereas the voltage of the bottom electrode of a gate to isolated p-well capacitor may be independently controlled.
The conventional method to form isolated p-wells is to add a deep n-well photoresist pattern and implant to a CMOS process flow. Typically, a CMOS process flow with an isolated p-well has two types of n-wells: core n-wells in which the core PMOS transistors are formed and a deep n-wells in which the isolated p-wells are formed.